法国专利FR3025649A1 METHOD OF POLARIZING A BURIED SOURCE PLAN OF A NON-VOLATILE MEMORY WITH VERTICAL SELECTION GRIDS

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专利摘要:
The invention relates to a method for controlling a memory comprising twin memory cells (C11, C12) formed in a semiconductor substrate (PW), each memory cell comprising a floating gate transistor (FGT) comprising a control gate state circuit (CG), in series with a selection transistor (ST) having a vertical selection control gate (SGC), common to both memory cells, and a source connected to a buried common source line (n0) to the memory cells, the drains of the floating gate transistors of a pair of twin memory cells being connected to the same bit line (BL), the method comprising a step of controlling a memory cell so as to make it busy for connecting the source line to a grounded bit line (BL, MBL, PBL) during a programming or reading step of another memory cell.
公开号:FR3025649A1
申请号:FR1458431
申请日:2014-09-09
公开日:2016-03-11
发明作者:Rosa Francesco La；Stephan Niel；Arnaud Regnier
申请人:STMicroelectronics Rousset SAS；
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专利说明:

[0001] The present invention relates to electrically erasable Programmable Read-Only Memory (EEPROM) electrically erasable and electrically erasable type non-volatile memories. The present invention more particularly relates to a non-volatile memory, comprising memory cells each comprising a floating gate transistor and a buried vertical selection transistor gate, shared with an adjacent memory cell called "twin". FIG. 1 is a circuit diagram of memory cells C11, C12 of the aforementioned type, belonging to two adjacent pages Pi, Pi + 1 of a memory plane. The memory cells C11, C12 are accessible for reading and writing via a bit line BL, a word line WL <i, i + 1> and CGL grid control lines, CGL . Each memory cell comprises a floating gate transistor FGT. The control gate CG of the transistor FGT of the cell C11 is connected to the gate control line CGL via a contact C4. The control gate CG of the transistor FGT of the cell C12 is connected to the gate control line CGL via a contact C4. The drain regions of the transistors FGT are connected to a bit line BL via C1 contacts. Each floating gate transistor FGT also has its source terminal connected to a source line SL via a respective selection transistor ST. The selection transistors ST share the same selection control gate SGC. The two memory cells C11, C12 are called "binoculars" because they share the same selection control gate SGC and the same bit line BL. The common control gate SGC is a vertical grid buried in a substrate receiving the memory plane, and is in contact with the source line SL formed by a region doped in depth in the substrate. The gate SGC is connected to a word line WL <i, i + 1> common to the two memory cells via a contact C3. The channel regions CH1, CH2 of the transistors FGT, ST are at the electric potential of the well 3025649 2 PW, as represented by dashed lines. Finally, the source line SL can be connected via a contact C5 to a general source line made in a metal level. FIG. 2 is a schematic sectional view of two twin memory cells C11, C12, comprising a selection transistor vertical gate SGC, common to the two memory cells. The memory cells C11, C12 are formed on a PW substrate of conductivity type P. The substrate is formed in a semiconductor plate called "wafer" WF. The PW casing is insulated from the rest of the WF wafer by an N-doped n-insulating layer which surrounds the entire casing. Each memory cell C11, C12 comprises a floating gate transistor FGT and a selection transistor ST. Each floating gate transistor FGT comprises a drain region n1, a source region n2, a floating gate FG, a state control gate CG, and a channel region CH1 extending under the floating gate FG between the drain regions n1 and source n2. The vertical selection gate SGC is buried in the substrate PW and isolated from the latter via an insulating layer D3, for example oxide SiO2, forming the gate oxide of the selection transistors ST. Region n2 extends along an upper edge of the buried vertical grid SGC. The SGC gate 20 reaches a source region nO common to the selection transistors ST, which thus forms a source line SL of the selection transistors ST. Each selection transistor ST thus comprises a drain region common to the source region n2 of the floating gate transistor FGT of its cell, the common source region n0, and a channel region CH2 extending vertically along the SGC grid between the n2 drain and nO source regions. Regions n1, n2 are generally formed by N-doping of the PW substrate. The floating gates FG are generally made of polycrystalline silicon of level 1, or "polyl", and are formed on the substrate PW by means of a tunnel oxide layer D1. The CG state control grids are generally made of polycrystalline silicon of level 2, or "poly2". Each state control gate CG is formed on one of the floating gates FG previously covered with an oxide layer D2. The SGC grid is formed in a trench filled with level 0 polycrystalline silicon, or "poly0", isolated from the substrate by the oxide layer D3. According to the selected manufacturing method, the conducting trench forming the SGC grid can have no electrical discontinuity. It can then be used directly as word line WL. The two memory cells C11, C12 are covered by a dielectric insulating material D0, which may also be SiO2 oxide. The drain regions n1 of the floating gate transistors FGT are connected to the same bit line BL via a contact C1 passing through the insulator DO. Figures 3 and 4 show the WF wafer in section and in view from above. Figures 3 and 4 show the layer nO which delimits the PW box in the wafer WF. The nO layer may be formed by two implantations of N-type dopants. A first implantation makes it possible to form a doped semiconductor horizontal layer which delimits the bottom of the PW box. A second implantation makes it possible to form vertical walls or "walls" 15 of the PW box. Figure 4 also shows the C5 contacts on the upper edge of the walls of the nO insulation layer. Since the nO layer is used as a source line, many C5 contacts are preferably provided all along the upper edge of the nO layer walls, as shown in the figure, in order to reduce its electrical resistance and favor the distribution of the nO layers. current lines in all directions. As indicated above, the contacts C5 make it possible to connect the nO layer to a general source line SL made in a metal level, or to control members of the source line voltage. It turns out that the nO layer has a significant resistivity.
[0002] Thus, FIG. 5 represents a curve of variation of the voltage VN of the layer n0 measured along a line crossing the wafer WF, when a current is injected at the center of the box PW, the contacts C5 being set to the mass. FIG. 5 shows that the voltage VN of the layer n0 increases by going from the edges of the box PW towards the center of the latter. The resistivity of the nO layer therefore precludes accurate control of the voltage applied to the source line, particularly when programming or reading a memory cell located among those furthest away from the contacts C5. It may be envisaged to form polarization taps of the nO layer in a central region of the PW box. However, the formation of such polarization taps is undesirable because of the large area they occupy. It is therefore desirable to improve the polarization of the nO layer without significantly reducing the usable wafer area for memory cell formation. Embodiments relate to a method of controlling a non-volatile memory on a semiconductor substrate, the memory comprising: bit lines, gate control lines, at least one word line, a source line formed into depth in the substrate, and pairs of twin memory cells, each having a first memory cell comprising a first floating gate transistor having a control gate connected to a first one of the gate control lines, a first conduction terminal connected to a first one of the bit lines and a second conduction terminal connected to the source line via a first selection transistor having a buried vertical selection control gate connected to the word line, and a second memory cell having a second floating gate transistor having a control gate connected to a second of the gate control lines, a first conduction terminal connected to the first bit line and a second conduction terminal connected to the source line through a second selection transistor sharing with the first selection transistor the selection control gate. According to one embodiment, the method comprises a step of controlling a memory cell of one of the pairs of memory cells, so as to make it pass to connect the source line to a line connected to the ground, during a step of programming another memory cell of the memory cell pairs. According to one embodiment, the method comprises a step of programming a memory cell to be programmed from one of the pairs of memory cells, by injecting hot electrons, via a programming current passing through the cell. memory to be programmed, by applying a first positive voltage to the bit line connected to the memory cell to be programmed and a second positive voltage to the gate control line connected to the memory cell to be programmed. According to one embodiment, the method comprises a step of reading a read memory cell of a pair of memory cells, comprising: applying a positive read voltage to the gate control line connected to the memory cell to read, and apply zero voltage to the gate control line connected to the memory cell of the memory cell to read.
[0003] According to one embodiment, a memory cell of one of the pairs of memory cells is dedicated to the grounding of the source line, the dedicated memory cell being kept busy, and the first conduction terminal of the gate transistor. floating point of the dedicated memory cell being connected to ground.
[0004] According to one embodiment, the programmed memory cell and the memory cell made conductive to ground the source line, are connected to the same word line, to a same gate control line and to bit lines. respective ones having respective ranks of different parities among the bit lines of the memory.
[0005] Embodiments also relate to a non-volatile memory on a semiconductor substrate, comprising: bit lines, gate control lines, at least one word line, a source line formed deep within the substrate, and pairs of twin memory cells, having a first memory cell comprising a first floating gate transistor having a control gate connected to a first one of the gate control lines, a first conduction terminal connected to a first one of the bit lines, and a second conduction terminal connected to the source line via a first selection transistor having a selection control gate connected to the word line, and a second memory cell having a second floating gate transistor having a control gate connected to a second of the gate control lines, a first conduction terminal connected to the first bit line and a second conduction terminal connected to the source line via a second selection transistor sharing with the first selection transistor the selection control gate, and means for programming the first memory cell independently of the second memory cell and vice versa. According to one embodiment, the memory is configured to control a memory cell of one of the memory cell pairs, so as to make it pass to connect the source line to a grounded line, during a step of 3025649 6 programming or reading of another memory cell pairs of memory cells. According to one embodiment, the memory is configured to program a memory cell to be programmed from one of the memory cell pairs by hot electron injection, via a programming current passing through the memory cell to be programmed. applying a first positive voltage to the bit line connected to the memory cell to be programmed and a second positive voltage to the gate control line connected to the memory cell to be programmed.
[0006] According to one embodiment, the memory is configured to read a memory cell to be read from a pair of memory cells, applying a positive read voltage to the gate control line connected to the memory cell to be read, and applying a zero voltage to the gate control line connected to the twin memory cell of the memory cell to be read.
[0007] According to one embodiment, a memory cell of one of the pairs of memory cells is dedicated to the grounding of the source line, the dedicated memory cell being kept conducting, and the first conduction terminal of the gate transistor. floating point of the dedicated memory cell being connected to ground.
[0008] According to one embodiment, each bit line is connected to ground via a grounding transistor, the grounding transistors of even-numbered bit lines being controlled via a third gate control line and the grounding transistors of odd-order bit lines being controlled through a fourth gate control line. According to one embodiment, each grounding transistor is connected to a bit line end section, the bit line end sections at each bit line end being alternately unconnected and connected to a bit line end section. Polarization plug of the source line. According to one embodiment, the memory comprises main bit lines and several memory plane sectors, each sector comprising local bit lines, and each local bit line being connected to one of the main bit lines by the Intermediate of a local bit line selection transistor, the local bit line selection transistors of each sector being controlled by a common gate control line. According to one embodiment, the selection control gate has two facing faces along which extend respectively a vertical channel region for the first selection transistor, and a vertical channel region for the second selection transistor. According to one embodiment, each pair of memory cells comprises: a first doped region extending along a first upper edge of the buried gate, forming a drain region of the selection transistor and a source region of the transistor floating-gate array, of a first memory cell of the pair of memory cells, a second doped region extending along a second upper edge of the buried gate opposite the first upper edge, forming a drain region of the selecting and a source region of the floating gate transistor, a second memory cell of the pair of memory cells, and a third doped region extending in depth in the substrate, in contact with two opposite lower edges of the gate buried, and forming a common source region of the memory selection transistors, each selection transistor of the pair of memory cells having 20 a vertical channel region extending from a respective side of the buried gate, between the first or second doped region and the third doped region. Exemplary embodiments of the invention will be described in the following, without limitation in connection with the accompanying figures, in which: FIG. 1 previously described is an electrical diagram of memory cells of an EEPROM memory, FIG. described above is a schematic cross-sectional view of two memory cells comprising a selection vertical grid SGC, common to the two memory cells, FIGS. 3 and 4 previously described represent, in section and in plan view, a wafer in which the cells are formed. 2, FIG. 5 described above represents a variation curve 35 of the voltage of a deep insulation layer, measured along a line 3025649 passing through the wafer represented in FIG. by a central point of the wafer, FIG. 6 is a schematic sectional view of the pair of memory cells of FIG. 2, illustrating a method of progra FIG. 7 is a schematic sectional view of the pair of memory cells of FIG. 2, illustrating a method for reading a memory cell, FIG. 8 schematically shows circuits of a plane. 10 memory in which the programming and reading methods can be implemented, according to one embodiment, Figure 9 schematically shows circuits of the memory plane of Figure 8, illustrating a method of polarization of the deep layer, during the In one embodiment of the invention, FIG. 10 shows circuitry of a memory array, illustrating another method of polarizing the deep layer, during programming of memory cells, according to another embodiment, the FIG. 11 is a top view of a right end region of two bit lines of the memory plane of FIG. 10, FIG. 12 is a diagrammatic section according to FIG. n plane AN of the bit line right end region, shown in FIG. 11, FIG. 13 is a top view of a left end region of two bit lines of the memory plane of FIG. 14 is a diagrammatic section along a plane BB 'of the left bit line end region, shown in FIG. 13, FIG. 15 represents circuitry of a memory plane, illustrating a method of polarizing the deep layer. in another embodiment, Fig. 16 is a schematic sectional view of a bit line region of the memory array of Fig. 15; Fig. 17 shows in plan view a region of a bit line of the plane. FIG. 6 shows the two twin memory cells C1, C12 of FIG. 2 and indicates voltage values applied to the memory cells during a "hot electron" programming operation of the cell. memory C11. During such programming, the two transistors FGT, ST of the memory cell C11 cooperate to inject electric charges into the floating gate FG. The selection transistor ST 5 has a conductive channel CH2 in which a current 11 (represented by arrows in FIG. 6) is formed comprising electrons with high kinetic energy, known as "hot electrons". When the current reaches the conducting channel CH1 of the floating gate transistor FGT, an injection zone is formed in which certain high energy electrons are injected into the floating gate FG under the effect of a transverse electric field generated by the voltage applied to the CG control grid. The transfer of charges from the substrate PW to the floating gate FG (programming) is therefore carried out via the selection transistor ST of the memory cell C1, and by applying a high potential difference (for example 10 V) on the gate FG floating, sufficient to obtain this transfer of charges. It turns out that the intensity of the current 11 varies as a function of the distance between the memory cell and the closest contact C5 (FIG. 4) of polarization (grounding) of the layer n0 forming the common source line. Due to this variation in current intensity, the programming conditions, and in particular the quantity of electrons injected into the floating gate FG of a programmed memory cell also varies according to the position of the memory cell in the box. PW. As a result, some memory cells that have been programmed can be read as erased. It may be noted that in the twin cell C12, a current 12 (represented by arrows in FIG. 6) also flows in the CH1 channel of the transistor FGT and in the CH2 channel of the transistor ST of the memory cell C12. The current 12 is insufficient to program the cell C12 because the control gate CG of the transistor FGT12 receives insufficient voltage (GND) to form an electric field capable of injecting electrons into the floating gate FG of this transistor. FIG. 7 represents the two twin memory cells C11, C12 of FIG. 2 and indicates values of voltages applied to the memory cells during the reading of the memory cell C11. Thus, during the reading of the memory cell C11, the common selection gate SGC of the two selection transistors ST of the twin memory cells, receives the read selection voltage Von. The selection transistors ST are therefore on. A current (represented by arrows in FIG. 7) flows in the channel region CH1 of the transistor FGT and in the channel region CH2 of the transistor ST of the memory cell C11. This current is representative of the threshold voltage of the transistor FGT which is itself representative of a programmed or erased state of the transistor, which depends on a quantity of electric charges stored in its floating gate FG. This current is sensed by a sense amplifier not shown in FIG. 7, which provides a bit data stored by the memory cell C11. Thus, the selection transistor ST of the twin memory cell C12 is also turned on, and its channel CH2 is conducting. If the transistor FGT of the memory cell C12 is in an over-erased state, it can also be on. As a result, the memory cell C11 will be seen bypassing and therefore erased, even if it is locked (programmed). To avoid this phenomenon, the voltage CGV applied to the control gate of the transistor FGT of the memory cell C12 can be set to a inhibition voltage Vinh which forces this transistor FGT in the off state and thus prevents it from driving even if it is in the over-erased state. This voltage is chosen equal to -2 V which is less than the threshold voltage of the floating gate transistors in the erased state. The state of the memory cell C11 is that which depends on the intensity of the current flowing in the CH2 channel of the selection transistor ST of the cell C11. Here again, this current depends on the bias voltage of the source region n0, which depends on the distance between the read memory cell 25 and the closest contact C5. This current variation can cause read errors. FIG. 8 represents an erasable memory per page comprising a memory plane MEM1 made in a PW box. The memory array comprises M x N memory cells forming pairs of memory cells C11, C12, each memory cell C11, C12 comprising a charge accumulation transistor FGT in series with a selection transistor ST. The selection transistors ST of each pair share a common selection grid SGC. The memory plane MEM1 comprises M pages P each comprising a row of N memory cells, and a CGL grid control line.
[0009] FIG. 8 shows first two pages P <O>, P <1> of ranks 0 and 1, and two pages P , P of ranks i and i + 1. The memory also comprises N bit lines BL <j, k>, each being connected to a memory cell of the same rank in each page. The bit lines BL <j, k> can be grouped into word columns k of m + 1 bit lines, j being between 0 and m. Figure 8 shows the bit lines of two word columns k and k + 1. Each bit line BL <j, k> is connected to the drain regions n1 of the floating gate transistors FGT of memory cells of the same rank j, k. Each CGL gate control line is connected to the state control gates CG of the floating gate transistors FGT of memory cells of same rank i. The memory plane MEM1 also comprises control lines WL <i, i + 1> of the selection transistors ST, which are connected to the common selection gates SGC of the memory transistors of the memory cells of two twin pages P <O> -P <1>, P -P . Thus, each control line WL <i, i + 1> of rank i, i + 1 is associated with the two pages P , P binoculars of ranks i and i + 1 and controls the transistors selection ST memory cells of these two twin pages. The voltages applied to the various control lines BL <j, k>, CGL , WL <i, i + 1> of the memory array MEM1 are provided by memory elements 20 according to an address of a memory. page to delete or a group of memory cells to read or program. These elements comprise: a CDEC column decoder, which connects the multiplexer MUX to the different bit lines, PGSW switches which apply to the different bit lines BL <j, k> connected to the memory cells of a word to be programmed B0-Bm, via the multiplexer MUX, the appropriate BLV <j, k> voltages during programming of the memory cells, - a word line pilot circuit WLDC which applies to the different lines of words WL <i, i + 1> the voltages SV <i, i + 1> for the common selection gates SGC of the selection transistors ST, and which applies to the different gate control lines CGL the gate control voltages CGV of the transistors to FGT floating gate, - an SLS source line switch which applies the SLV source line voltage to the nO layer forming a source plane, 3025649 12 - a PWS box switch which applies the substrate voltage VB to the PW box - SA reading amplifiers ("Sense Amplifiers"), which apply to the different bit lines BL <j, k> via the multiplexer MUX the appropriate voltages BLV <j, k> during the reading of memory cells, and supply the bits B0-Bm of a binary word read in the memory, and these bodies are configured to provide the voltages capable of performing programming operations, reading and erasure. In particular, during a programming operation, the WLDC word line driver 10 supplies the programming voltage to the gate control line CGL connected to the memory cells of the word line pair WL <i, i + 1>. including memory cells program. During an erase operation, the WLDC word line driver may provide an erase voltage to the gate control line connected to the twin page memory cells P -P , causing erasing all memory cells from these two twin pages. During a read operation, the sense amplifiers SA provide a reading bias voltage to the bit lines BL of the memory cells to be read. FIG. 9 represents the memory array formed in the PW box, during a programming operation of the memory cell C12. According to one embodiment, certain memory cells of the memory plane are used to polarize the nO layer. In the embodiment of FIG. 9, bit lines BL are connected to ground via a DST bit line selection transistor. According to one embodiment, the gates of the DST transistors are connected to CLP <0>, CLP <1> bit line selection lines, the gates of the DST transistors of the even rank bit lines being connected to the line. selecting CLP <0> and the gates of the DST transistors of odd-rank bit lines being connected to the CLP selection line <1>. The CLP <0> and CLP <1> selection lines may be controlled by the WLDC decoder simply based on the parity of the memory cell access address word. In the example of FIG. 9, the memory cell C12 is being programmed. For this purpose, the voltage BLV <1, k> of the odd bit line BL connected to the memory cell C12 is set at 4 V. The other bit lines 35 are subjected to a floating potential HZ. The voltage CGV of the gate control line CGL connected to the memory cell C12 is set at 10 V. The voltage SV <i, i + 1> of the line of the word WL <i, i + 1> connected to the memory cell C12 is set to 2 V. The other CGL grid control lines and the other word lines are grounded (0 V). As a result, the memory cells connected to the CGL gate control line are on. Since the memory cell C12 is connected to a bit line of odd rank, the selection line CLP <1> of the DST transistors connected to the bit lines BL of odd rank is set to a sufficiently low voltage CLV <1> (at ground level). ) to block these transistors, and the CLP selection line <0> of the DST transistors connected to the even-rank bit lines BL is set to a positive CLV <0> voltage, for example between 3 and 5 V to make these transistors. As a result, the even-numbered bit lines BL are grounded while the other bit lines remain at a floating potential. Consequently, the memory cells connected to the gate control line CGL and the even-numbered bit lines are conducting and thus bring the source plane n0 to ground at points situated at a distance from the edge. PW box, and in particular near the memory cell to program. Of course, when programming a memory cell 20 connected to a bit line of even rank, the selection line CLP <0> is set to a sufficiently low voltage (at ground level) to block the DST transistors connected to the even-numbered bit lines and the CLP selection line <1> is set to a positive voltage (for example between 3 and 5 V) to unblock the DST transistors connected to the odd-rank bit lines. If the programming operations are performed by word, they can be carried out in two successive steps, one to program the memory cells connected to even-rank bit lines, and the other to program the memory cells connected to lines. bit of 30 odd rank. Another solution could be to use the word decoder to connect to the ground only bit lines not belonging to a word to be programmed, or all these lines of bit. FIG. 10 shows a memory plane MEM2 formed in a PW box, during a programming operation of a memory cell C22 belonging to a pair of twin memory cells C21, C22. According to one embodiment, each bit line BL of the memory array is divided into a plurality of local bit lines LBL connected to a main bit line MBL via a local bit line selection transistor BST. In the example of FIG. 10, each bit line is divided into a first and a second local bit line LBL. Thus, this division of the local bit lines defines in the memory plane two sectors of memory cells, namely a first sector SM1 of memory cells connected to the first local bit lines, and a second sector SM2 of memory cells connected to the second lines of memory. local bit. The memory plane 10 PM1 comprises the CGL <0> grid control lines to CGL and the word lines WL <0.1> to WL <p-1, p>, and the memory plane PM2 comprises the lines CGL to CGL <n> and the word lines WL to WL <n-1, n>. The gates of the BST transistors connected to the first local bit lines are connected to a sector selection line PS <0>, and the gates of the BST transistors connected to the second local bit lines are connected to a PS sector selection line. <1>. Furthermore, according to one embodiment, each main bit line MBL is connected to ground via a DST selection transistor. In the example of FIG. 10, this connection to ground is made via connections to the ground of polarization taps of the layer n0. The gates of the DST transistors are connected to CLP <0>, CLP <1> bit line selection lines, the gates of the DST transistors of the even rank main bit lines MBL being connected to the CLP selection line < 0>, and the gates of the DST transistors of the main bit lines MBL of odd rank being connected to the selection line CLP <1>. The CLP <0> and CLP <1> selection lines may be controlled by the WLDC decoder depending on the parity of the memory cell access address word.
[0010] In the example of FIG. 10, the memory cell C22 is being programmed. For this purpose, the voltage BLV <1, k> of the main bit line of odd rank MBL connected to a memory cell C22 is set at 4 V. The other main bit lines MBL are subjected to a floating potential HZ. The PSV voltage <0> of the PS <0> selection line of the first PM1 sector to which the memory cell C22 belongs is set to a positive voltage (for example between 3 and 5 V) to turn on the BST transistors of the first PM1 sector. The selection line PS <1> of the second sector PM2 is set at a sufficiently low voltage (at ground level) to block the BST transistors of the second sector PM2. The voltage CGV of the gate control line CGL connected to the memory cell C22 is set at 10 V. The voltage SV <p-1, p> of the word line WL <p-1 , p> connected to the memory cell C22 is set to 2 V. The other CGL grid control lines and the other word lines WL are grounded (0 V). As a result, the memory cells connected to the gate control line CGL are all on. The CLP selection line <1> of the DST transistors connected to the main bit lines MBL of odd rank is set to a sufficiently low voltage (at ground), so that these transistors are blocked. The CLP selection line <0> of the DST transistors connected to the main bit lines MBL of even rank is set to a positive voltage, for example between 3 and 5 V, for these transistors to be on. As a result, even main bit lines MBL are grounded while the other bit lines remain at a floating potential. Therefore, the memory cells of the first sector PM1 connected to the gate control line CGL and connected to the main bit lines MBL of even rank are passing and thus put the source plane n0 to ground at points located at a distance from the edge of the PW box. It should be noted that the transistor DST of the main bit line MBL to which the memory cell C22 is connected is blocked, and therefore the positive voltage BLV <1, k> (set at 4 V) of this bit line is not short circuit with the ground. Of course, if the memory cell to be programmed is connected to a main bit line of even rank, the main bit lines of odd rank are grounded by the DST transistors controlled by the line CLP <1>.
[0011] Figs. 11 and 12 show a bit line straight end region of the memory array of Fig. 10, and Figs. 13 and 14 are a corresponding left end region. In particular, FIGS. 11 and 13 show two rows of memory cells along two bit lines BL <j>, BL <j + 1>. Figure 12 shows the bit line BL <j>, and Figure 302 564 9 16 14, the bit line BL <j + 1>. For the sake of clarity, FIGS. 11 and 13 do not show a main bit line MBL. Each BL <j> bit line end region, BL <j + 1> comprises a first (Fig. 14) or a last (Fig. 12) pair of ECL memory cells (as shown in Fig. 2), connected to a local bit line LBL, a local bit line selection transistor BST connecting the local bit line LBL to a link C6 connected to a main bit line MBL, a selection transistor DST, and a section of bit line end DBL1, DBL2, DBL3, DBL4 decoupled from a local bit line and under which unused DCL memory cell pairs are formed due to possible edge effects. According to one embodiment, a DBL1, DBL4 of the two right and left bit line bit sections of each bit line BL <j>, BL <j + 1> is connected to ground, on the right ( FIG. 12 and row of memory cells located at the top in FIG. 11) for the main bit lines MBL of rank having a certain parity, and on the left (FIG. 14 and row of memory cells situated at the bottom in FIG. 13) for the main bit lines MBL of rank having another parity. The bit line end sections DBL1, DBL4 are connected to the main bit line MBL formed above via a link C7 and one of the 20 DST transistors connected to the link C6 and at the C7 link. In the example of FIGS. 11 to 14, the ground connection of the bit line end sections DBL1, DBL4 is carried out by extending the bit line end sections to a C5 polarization contact of FIG. deep layer nO. It should be noted that in the example of FIGS. 12 and 14, the selection transistors DST and BST have two superposed grids, such as the FGT transistors of the memory cells, for reasons of simplicity of manufacture. However, the transistors DST, BST are used as conventional selection transistors, the lower gate corresponding to the floating gate being controlled directly. The selection transistors DST, BST could be made with a simple gate like the selection transistors ST. FIG. 15 represents a memory plane MEM3 formed in a PW box, according to another embodiment. Figure 15 shows voltages supplied to the memory array during a programming operation of a memory cell of a pair of twin memory cells CL. Here again, each bit line BL of the memory array is divided into a plurality of local bit lines LBL connected to a main bit line MBL via a local bit line selection transistor BST. Thus, this division of the local bit lines defines in the memory plane several sectors PM11, PM12 of memory cells, gathering each of the memory cells connected to local bit lines of the same rank, that is to say connected to the same word lines WL <i, i + 1>. The gates of the BST transistors connected to the local LBL bit lines of the PM11 sector are connected to a sector selection line PS <O>, and the gates of the BST transistors 10 connected to the local bit lines LBL of the PM12 sector are connected to a sector selection line PS <1>. According to one embodiment, the memory array MEM3 comprises a PCL1, PCL2 row of memory cells, or pairs of dedicated PCL memory cells, which are used to connect the source plane n0 to the ground. For this purpose, the memory cells of the rows PCL1, PCL2 are polarized so as to pass and the drain terminals of the floating gate transistors FGT of the memory cells of each row PCL1, PCL2 are connected to the ground, directly or by the intermediate of a PBL bit line section. The gates of the transistors FGT of each row PCL1, PCL2 receive a positive voltage, for example between 3 and 5 V, and the gates of the selection transistors ST of each row PCL1, PCL2 receive a positive voltage, for example fixed at 2 V. The rows PCL1, PCL2 may be formed between the sectors PM11, PM12, as illustrated in FIG. 15. FIGS. 16 and 17 show a bit line region of the memory plane MEM3 of FIG. 15, and in particular, a pair of twin memory cells CL of each sector PM11, PM12 and a pair of PCL memory cells of the rows PCL1, PCL2, between the two sectors PM11, PM12. The region between the two sectors PM11, PM12 comprises two LBL local bit line selection transistors LBL connecting the main bit line MBL to a respective local LBL bit line of sectors PM11, PM12, and between transistors BST two transistors DT not used, and the pair of PCL twin memory cells disposed between the transistors DT. In the example of FIGS. 16 and 17, the selection transistors DST and BST have two superposed grids, such as the FGT transistors of the memory cells, for reasons of simplicity of manufacture. However, the transistors DST, BST are also used as conventional selection transistors, the lower gate corresponding to the floating gate being controlled directly. The selection transistors DST, BST could be made with a simple gate like the selection transistors ST. Similarly, the double gate transistors of the PCL cell pairs (FIGS. 15, 16 and 17) could also be fabricated with a simple gate and are used as selection transistors. For this purpose, the voltage at 3 V in Figure 15 is provided directly to the lower gate. It will be apparent to those skilled in the art that the present invention is susceptible to various alternative embodiments and applications. In particular, the invention also covers combinations of the embodiments described above. Thus, in the embodiments described with reference to FIGS. 8 to 14, memory cells dedicated to the polarization or grounding of the nO source plane can be provided. Furthermore, the invention can also be applied to a memory in which the programming operations are performed by the Fowler-Nordheim effect. Also, it is also obvious that the voltages indicated in FIGS. 6, 7, 9, 10 and 15 are only provided by way of example, and that other voltages can be supplied to the various memories previously described. these voltages may depend in particular on the nature of the substrate and the different doped regions.

权利要求:
Claims (14)
[0001]
REVENDICATIONS1. A method of controlling a nonvolatile memory on a semiconductor substrate (PW), the memory comprising: bit lines (BL), gate control lines (CGL , CGL ), at least one word line (WL <i, i + 1>), a source line (nO) formed deep within the substrate, and pairs of twin memory cells (C11, C12, C21, C22), each having a first memory cell comprising a first floating gate transistor (FGT) having a control gate (CG) connected to a first of the gate control lines (CGL ), a first conduction terminal connected to a first of the lines bit and a second conduction terminal connected to the source line via a first selection transistor (ST) having a buried vertical selection control (SGC) gate connected to the word line, and a second memory cell comprising a second floating gate transistor (FGT) having a connected control gate one second of the gate control lines (CGL ), a first conduction terminal connected to the first bit line and a second conduction terminal connected to the source line via a second selection transistor (ST) sharing with the first selection transistor the selection control gate, characterized in that it comprises a step of controlling a memory cell of one of the pairs of memory cells, so as to passing through to connect the source line (n0) to a grounded line (BL, MBL, PBL) during a programming or reading step of another memory cell (C12, C22, C32) of memory cells.
[0002]
2. Method according to claim 1, comprising a step of programming a memory cell (C12, C22, C32) to be programmed from one of the pairs of memory cells, by injection of hot electrons, via a programming current (11) passing through the memory cell to be programmed, applying a first positive voltage to the bit line (BL, LBL) connected to the memory cell to be programmed and a second positive voltage to the gate control line (CGL ) connected to the memory cell to be programmed.
[0003]
The method of claim 1 or 2, comprising a step of reading a read memory cell of a pair of memory cells, comprising: applying a positive read voltage to the gate control line connected to the memory cell to read, and apply zero voltage to the gate control line connected to the twin memory cell of the memory cell to read.
[0004]
4. Method according to one of claims 1 to 3, wherein a memory cell (PCL1, PCL2, PCL) of one of the pairs of memory cells is dedicated to the grounding of the source line (n0), the dedicated memory cell 15 being kept busy, and the first conduction terminal of the floating gate transistor (FG) of the dedicated memory cell being connected to ground.
[0005]
5. Method according to one of claims 1 to 4, wherein the programmed memory cell (C12, C22, C32) and the memory cell made to pass to ground the source line (n0), are connected to a same word line (WL <i, i + 1>), to the same grid control line (CGL ) and to respective bit lines (BL, MBL) having respective ranks of different parities among the bit lines of the memory. 25
[0006]
6. Non-volatile memory on a semiconductor substrate (PW), comprising: bit lines (BL), gate control lines (CGL , CGL ), at least one line of word (WL <i, i + 1>), a source line (nO) formed in depth in the substrate, and pairs of twin memory cells (C11, C12, C21, C22), comprising a first memory cell comprising a first floating gate transistor (FGT) having a control gate (CG) connected to a first of the gate control lines (CGL ), a first conduction terminal 3025649 21 connected to a first of the bit lines and a first a second conduction terminal connected to the source line via a first selection transistor (ST) having a selection control gate (SGC) connected to the word line, and a second memory cell having a second transistor with 5 floating gate (FGT12) having a control gate connected to a second of the control lines of gri lle (CGL ), a first conduction terminal connected to the first bit line and a second conduction terminal connected to the source line via a second selection transistor (ST12, ST3) sharing with the first selection transistor the selection control gate, and means for programming the first memory cell independently of the second memory cell and vice versa, characterized in that it is configured to control a memory cell of one of the pairs of memory cells, so as to make it pass to connect the source line (nO) to a line (BL, MBL, PBL) connected to the ground, during a programming or reading step of another memory cell (C12, C22, C32) pairs of memory cells.
[0007]
Memory according to claim 6, configured to program a memory cell (C11, C21, C22) to be programmed from one of the pairs of memory cells by hot electron injection, via a programming current ( 11) passing through the memory cell to be programmed, applying a first positive voltage to the bit line (BL, LBL) connected to the memory cell to be programmed and a second positive voltage to the gate control line (CGL ) connected to the memory cell to be programmed.
[0008]
A memory according to claim 6 or 7, configured to read a read memory cell of a pair of memory cells, applying a positive read voltage to the gate control line connected to the memory cell to be read, and applying a zero voltage to the gate control line connected to the twin memory cell of the memory cell to be read.
[0009]
9. Memory according to one of claims 6 to 8, in which a memory cell (PCL1, PCL2, PCL) of one of the pairs of memory cells is dedicated to the grounding of the source line (n0). , the dedicated memory cell being held on, and the first conduction terminal of the floating gate transistor (FG) of the dedicated memory cell being connected to ground. 5
[0010]
The memory according to one of claims 6 to 9, wherein each bit line (BL, MBL) is connected to ground via a grounding transistor (DCL), the setting transistors the ground of even-rank bit lines being controlled via a third gate control line (CLP <O>) and the grounding transistors of odd-order bit lines being controlled by via a fourth grid control line (CLP <1>).
[0011]
The memory of claim 10, wherein each grounding transistor (DCL) is connected to a bit line end section (DBL1, DBL2, DBL3, DBL4), the line end sections. bit at each bit line end (MBL) being alternately unconnected and connected to a bias tap (C5) of the source line (n0). 20
[0012]
The memory according to one of claims 6 to 11, comprising main bit lines (MBL) and a plurality of memory array sectors (MP1, MP2, MP11, MP12), each sector comprising local bit lines (LBL), and each local bit line being connected to one of the main bit lines through a local bit line selection transistor (BST), the local bit line selection therethrough of each sector being controlled by a common gate control line (PS <0>, PS <1>).
[0013]
13. Memory according to one of claims 6 to 12, wherein the selection control gate (SCG) has two facing faces along which extend respectively a vertical channel region (CH2) for the first transistor. selection (ST), and a vertical channel region (CH2) for the second selection transistor (ST). 3025649 23
[0014]
The memory according to one of claims 6 to 13, wherein each pair of memory cells (C11, C12) comprises: a first doped region (n2) extending along a first upper edge of the buried gate ( SGC), forming a drain region of the selection transistor (ST) and a source region of the floating gate transistor (FGT), of a first memory cell (C11) of the pair of memory cells, a second doped region (n2) extending along a second upper edge of the buried gate opposite the first upper edge, forming a drain region of the selection transistor (ST) and a source region of the floating gate transistor (FGT) , a second memory cell (C12) of the pair of memory cells, and a third doped region (nO) extending in depth in the substrate, in contact with two opposite lower edges of the buried gate, and forming a common source region of the transistor transistors selecting (ST) the memory, each selection transistor (ST) of the pair of memory cells having a vertical channel region (CH2) extending from a respective side of the buried gate between the first or second region doped and the third doped region.

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引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US5182725A|1987-11-20|1993-01-26|Mitsubishi Denki Kabushiki Kaisha|Nonvolatile semiconductor memory device with reduced variation in source potential of floating gate type memory transistor and operating method therefor|

US20040130947A1|2003-01-02|2004-07-08|Der-Tsyr Fan|Flash memory with trench select gate and fabrication process|

US20080165582A1|2006-09-05|2008-07-10|Catalyst Semiconductor, Inc.|Scalable Electrically Eraseable And Programmable Memory|

US20100265765A1|2009-04-20|2010-10-21|Bo-Young Seo|Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same|

US20130229875A1|2012-03-05|2013-09-05|Stmicroelectronics Sas|Method of reading and writing nonvolatile memory cells|

US20140036591A1|2012-07-31|2014-02-06|Renesas Electronics Corporation|Memory device|

JP3999900B2|1998-09-10|2007-10-31|株式会社東芝|Nonvolatile semiconductor memory|

US6788576B2|2002-10-28|2004-09-07|Tower Semiconductor Ltd.|Complementary non-volatile memory cell|

JP4907563B2|2008-01-16|2012-03-28|パナソニック株式会社|Semiconductor memory device|

US8274829B2|2008-06-09|2012-09-25|Aplus Flash Technology, Inc.|Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS|

WO2011049628A1|2009-10-23|2011-04-28|Aplus Flash Technology, Inc.|Novel punch-through free program scheme for nt-string flash design|

WO2012033533A1|2010-09-09|2012-03-15|Aplus Flash Technology, Inc.|Compact flotox-based combo nvm design without sacrificing endurance cycles for 1-die data and code storage|

US8923049B2|2011-09-09|2014-12-30|Aplus Flash Technology, Inc|1T1b and 2T2b flash-based, data-oriented EEPROM design|

WO2013079020A1|2011-12-02|2013-06-06|Tsinghua University|Nor flash memory array structure, mixed nonvolatile flash memory and memory system comprising the same|

US8901634B2|2012-03-05|2014-12-02|Stmicroelectronics Sas|Nonvolatile memory cells with a vertical selection gate of variable depth|

JP5627624B2|2012-03-16|2014-11-19|株式会社東芝|Programmable logic device|

US9142306B2|2013-01-11|2015-09-22|Atmel Corporation|Selecting memory cells using source lines|

JP2015185180A|2014-03-20|2015-10-22|株式会社東芝|configuration memory|

US9508396B2|2014-04-02|2016-11-29|Ememory Technology Inc.|Array structure of single-ploy nonvolatile memory|

KR102185079B1|2014-04-21|2020-12-01|에스케이하이닉스 주식회사|Non-volatile memory device and method of operating the same|FR3021806B1|2014-05-28|2017-09-01|St Microelectronics Sa|METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID|

CN108806751B|2017-04-26|2021-04-09|中芯国际集成电路制造有限公司|Multi-time programmable flash memory cell array, operation method thereof and memory device|

US10276582B2|2017-08-21|2019-04-30|Globalfoundries Singapore Pte. Ltd.|High coupling ratio split gate memory cell|

US10847210B2|2018-04-09|2020-11-24|Taiwan Semiconductor Manufacturing Company, Ltd.|Memory device with fly word line|

US10734398B2|2018-08-29|2020-08-04|Taiwan Semiconductor Manufacturing Co., Ltd.|Flash memory structure with enhanced floating gate|

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优先权:

申请号 | 申请日 | 专利标题

FR1458431A|FR3025649B1|2014-09-09|2014-09-09|METHOD FOR POLARIZING A BURIED SOURCE PLAN OF A NON-VOLATILE MEMORY WITH VERTICAL SELECTION GRIDS|FR1458431A| FR3025649B1|2014-09-09|2014-09-09|METHOD FOR POLARIZING A BURIED SOURCE PLAN OF A NON-VOLATILE MEMORY WITH VERTICAL SELECTION GRIDS|

US14/810,283| US9368215B2|2014-09-09|2015-07-27|Method for biasing an embedded source plane of a non-volatile memory having vertical select gates|

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